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what is BiFAST?

BiFAST is a high-tech startup that enables active copper cables offering reduced cost, size and weight for short reach (up to 10m), high speed (+100G) data center cables.

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Pushing the boundaries of serial electrical communication

Performance through simplicity

By using duobinary a simple transmitter (NRZ transmitter) and receiver architecture can be used which has led to achieving serial data rates up to 100 Gb/s at low power consumption. Moreover the duobinary modulation allows us to use well-known NRZ CDR techniques.

Backwards compatible

Duobinary is inherently compatible with NRZ in our implementation which means that NRZ transmission can be realized with our duobinary chipset with at least half the data rate of the duobinary data rate across a certain channel.

Loss to our advantage

Unlike other modulation formats duobinary can use a portion of the loss present in the channel to create the desired waveform, reducing the needed equalization.

Crosstalk tolerant

By nature duobinary is less prone to crosstalk in comparison to other advanced modulation formats like PAM4 due to only having three levels.

Low power consumption

Since duobinary requires a very limited set of building blocks at the transmitter and receiver and due to the nature of duobinary signaling, the BiFAST technology is intrinsically low power.

Learn more

Want to know more about the basics of duobinary? We've added a quick guide illustrating the fundamentals of duobinary signaling...

Read more

In the news

BiFAST demonstration @ imec Technology Forum featured on EE Times

The live demonstration of the BiFAST OSFP cable at imec's Technology Forum (ITF) did not go unnoticed, and got featured on EE Times: [article]

BiFAST demonstrates 100 Gb/s OSFP cable at DesignCon 2017 on Amphenol booth

During the DesignCon 2017 exhibition, BiFAST demonstrated a live running 100 Gb/s per channel OSFP cable, displaying the real-time BER measurements. [demonstrators]

BiFAST shows 56 Gb/s over Samtec ZRay interposer at DesignCon 2017

The performance of the Samtec ZRay interposer was shown during the DesignCon 2017 exhibition using a BiFAST transmitter IC to generate 56 Gb/s NRZ and displaying the NRZ eye on an oscilloscope. [demonstrators]

Xilinx, Keysight and Cisco team up with BiFAST for DesignCon 2017 paper

To fill the void in the industry to model and simulate duobinary signaling, Xilinx, Keysight and Cisco have teamed up with BiFAST to develop an IBIS-AMI model of link systems using duobinary signaling. Furthermore, Keysight published this as a White Paper. [publications]

BiFAST CEO Timothy De Keulenaer receives Nokia Bell Scientific Prize

For his PhD thesis A Duobinary Receiver Chip for 84 Gb/s Serial Data Communication, BiFAST CEO Timothy De Keulenaer was awarded the Nokia Bell Scientific Prize by the FWO/FNRS on November 30th 2016, in recognition of the PhD thesis that brings the most original contribution in the field of information and communication technology.

ECOC2016 Post Deadline Paper enabled by BiFAST

The ECOC 2016 post deadline Paper First Demonstration of Real-Time 100 Gbit/s 3-Level Duobinary Transmission for Optical Interconnects showed the versatility of the BiFAST chipset, using the ICs to set up a 100 Gb/s optical interconnect. The conference paper also resulted in a publication in the Journal of Lightwave Technology, see our [publications].

who are we?

Timothy De Keulenaer, Ph.D.

Chief Executive Officer

Graduated in 2010 as a Master of Science in applied electrical engineering at Ghent University where he received his Ph.D. degree in applied electrical engineering in 2015. Timothy has gathered four years of experience in the field of high-speed transceivers and duobinary. He is the author of several papers on high-speed SERDES systems and the co-inventor of three patents related to duobinary.

Arno Vyncke, Ph.D.

Chief Commercial Officer

Graduated in 2010 as a Master of Science in applied electrical engineering at Ghent University, his expertise encompasses FPGAs and the integration of VCOs and CDRs for 40Gb/s. His role within the BiFAST project mainly involves the exploration of business opportunities and the development of digital blocks in the next transceiver generation.

Ramses Pierco, Ph.D.

Vice President of Engineering

Graduated in 2010 as a Master of Science in applied electrical engineering at Ghent University where he received his Ph.D. degree in applied electrical engineering in 2015. He is responsible for the technology development within the BiFAST project in which his focus lies on further integration of a duobinary transceiver.

Renato Vaernewyck, Ph.D.

Senior Engineer

Graduated in 2010 as a Master of Science in applied electrical engineering at Ghent University where he received his Ph.D. degree in applied electrical engineering in 2014. He leads the R&D and testing efforts within the BiFAST project and is currently working on the further development of a complete duobinary transceiver.

chipset

Within the BiFAST project a duobinary transceiver chipset has been developed which has achieved data rates ranging from 40 Gb/s up to 100 Gb/s across several types of channels (backplane, twinaxial cable, ...). Information on this chipset can be found in the datasheet and application note. A commercial (packaged) version of this chipset will become available in 2017.

BFDC-100TRx-ES1 Transceiver [datasheet]
BFDC-100Tx-ES1 Transmitter [datasheet]
BF-AN001 100 Gb/s serial duobinary (4:1) across twinaxial cable channel [application note]

demonstrators

100 Gb/s OSFP cable at DesignCon 2017
(Santa Clara, USA Jan 2017)

In collaboration with Amphenol, BiFAST showed single-lane 100 Gb/s communication running live over a 1m OSFP cable built with Amphenol SpectraStrip TwinAx during DesignCon 2017 at the Amphenol booth.

56 Gb/s ZRay interposer DesignCon 2017
(Santa Clara, USA Jan 2017)

Using the BiFAST transceiver, 56 Gb/s NRZ transmission was demonstrated across a Samtec ZRay interposer showing live NRZ eye diagrams at the Samtec booth during DesignCon 2017.

56 Gb/s and 100 Gb/s at DesignCon 2016
(Santa Clara, USA Jan 2016)

At DesignCon 2016 a new standard in high serial data rates was set by achieving 100Gb/s across a 1.5 m twinaxial 26AWG cable (highest serial data rate ever shown across copper). Furthermore the performance of our current duobinary chipset was confirmed by achieving 56 Gb/s across a 20 inch backplane channel.

56 Gb/s at DesignCon 2015
(Santa Clara, USA Jan 2015)

The DesignCon 2015 demonstrator showed the superior performance of duobinary on high loss channels by achieving 56 Gb/s over a backplane with 35 dB loss at Nyquist (28 GHz).

84 Gb/s at Bell Labs Future X days
(Antwerp Oct 2014, Stuttgart Nov 2014)

At the Bell Labs Future X days a record high serial data rate of 84 Gb/s by means of duobinary was demonstrated to the world. This was done over a channel with 15 dB of loss at Nyquist (42 GHz).

publications

2017

IBIS-AMI Modeling and Simulation of Link Systems using Duobinary Signaling [paper] [presentation] [published as Keysight White Paper]
H. Zhang, F. Rao, T. De Keulenaer, K. Ly, R. Pierco and G. Zhang, DesignCon 2017

2016

Real-Time 100 Gb/s Transmission using 3-Level Electrical Duobinary Modulation for Short-reach Optical Interconnects [paper]
M. Verplaetse, R. Lin, J. Van Kerrebrouck, O. Ozolins, T. De Keulenaer, X. Pang, R. Pierco, R. Vaernewyck, A. Vyncke, R. Schatz, U. Westergren, G. Jacobsen, S. Popov, J. Chen, G. Torfs, J. Bauwelinck and X. Yin, Journal of Lightwave Technology

First Demonstration of Real-Time 100 Gbit/s 3-Level Duobinary Transmission for Optical Interconnects [paper]
X. Yin, M. Verplaetse, R. Lin, J. Van Kerrebrouck, O. Ozolins, T. De Keulenaer, X. Pang, R. Pierco, R. Vaernewyck, A. Vyncke, R. Schatz, U. Westergren, G. Jacobsen, S. Popov, J. Chen, G. Torfs and J. Bauwelinck, ECOC 2016 - Post Deadline Paper

On-chip transmitter and receiver front-ends for ultra-broadband wired and optical-fiber communications [paper]
J. Bauwelinck, W. Soenen, B. Moeneclaey, M. Vanhoecke, R. Pierco, R. Vaernewyck, T. De Keulenaer, G. Roelkens, G. Torfs, X. Yin and P. Demeester, Optical Fiber Communications Conference and Exhibition (OFC) 2016

100 Gb/s Serial Transmission over copper using Duo-binary Signaling [paper] [presentation]
J. Van Kerrebrouck, T. De Keulenaer, J. De Geest, R. Pierco, et al. DesignCon 2016

A Wide-Band, 5-Tap Transversal Filter With Improved Testability for Equalization up to 84 Gb/s [IEEEXplore]
Y. Ban, T. De Keulenaer, Z. Li, J. Van Kerrebrouck et al. IEEE Microwave and Wireless Components Letters, Vol. 25, No. 11, October 02, 2015, pp. 739-741

Experimental evaluation of NRZ and duobinary up to 48 Gbit/s for electrical backplanes [IEEEXplore]
Y. Ban, T. De Keulenaer, G. Torfs, J.H. Sinsky et al. IET Electronic Letters, Vol. 51, No. 8, April 16, 2015, pp. 617-619

2015

56+ Gb/s Serial Transmission using Duobinary Signaling [paper] [presentation]
T. De Keulenaer, J. De Geest, G. Torfs, J. Bauwelinck, Y. Ban, J. Sinsky and B. Kozicki, DesignCon 2015

84 Gbit/s SiGe BiCMOS duobinary serial data link including Serialiser/Deserialiser (SERDES) and 5-tap FFE [IEEEXplore]
T. De Keulenaer, G. Torfs, Y. Ban, R. Pierco, et al. IET Electronic Letters, Vol. 51, No. 4, February 19, 2015, pp. 343-345